pAVR - RISC microcontroller
This project implements an 8 bit controller that is compatible with Atmel's
AVR architecture, using VHDL
(Very High speed integrated circuits Hardware Description Language).
pAVR is a maximally featured AVR. It is configurable enough to be able to
simulate most AVR family controllers.
The documentation (ver 0.42) provides most
implementation details, while the
development package (ver 0.35) contains
everything one needs to take over pAVR.
- 6 pipeline stages
- 1 clock/instruction for most instructions
- estimated clock frequency: ~50 MHz & 0.5 um; assuming that Atmel's core
runs at 15 MHz & 0.5 um. That's ~3x Atmel original core's performance.
- estimated MIPS at 50 MHz: 28 MIPS (typical), 50 MIPS (peak). That's ~3x
Atmel original core's performance. At 15 MHz, Atmel's core has 10 MIPS
typical, and 15 MIPS peak.
- CPI (clocks per instruction): 1.7 clocks/instruction (typical),
1 clock/instruction (peak). That's ~0.75x (typical), 1.00x (peak) Atmel
original core's performance.
- up to 32 interrupt sources. Each interrupt has programmable priority
and jump address.
- heavily parameterized design that permits flexible costumization
- pAVR architecture is rather computational-friendly than control-friendly.
I designed parts of a Network Processor.
My task was to design two modules: a Header Modifier and a Protocol Decoder.
I built them in VHDL.
These two modules implemented in hardware search and recognize/modify
algorithms that allowed the Network Processor to identify and alter network packets
in real time, according to specific instructions stored in a memory.
The modules were synthesized with NEC's 0.25 um technology. The results showed
that they could run at 166MHz. However, this limit was imposed by the available
memories. The critical path in the modules themselves corresponded to at least
200MHz operating frequency, which is not bad for 0.25 um technology.
I have built a DMA controller core in VHDL.
It is synthesizable and parameterized.
It's main feature is its efficient scheme of allocating resources to multiple DMA channels.
Rather than prioritizing channels by an absolute priority, each channel is assigned
fraction of the available bandwidth through local buses.
This way, all channels transfer data quasi-simultaneousely, providing hardware
support for multitasking.
The documentation can be found here .